(1) Field of the Invention
The present invention relates to a pseudo-synchronization prevention method in an SDH transmission mode, a pseudo-synchronization preventing SDH transmission system, and a transmitter-receiver in the pseudo-synchronization preventing SDH transmission system, all of which are suitable for use in a transmission unit to which the SDH transmission mode is applied.
(2) Description of the Related Art
According to an SDH (Synchronous Digital Hierarchy) transmission mode defined in ITU-T, at a time of data transmission from one terminal apparatus to another terminal apparatus, data link is enabled between the terminal apparatus by using a container [minimum unit of transmission information such as F2 byte (UserCH)] in a VC (Virtual Container) path, that is, a clear channel provided to a user.
In the SDH transmission mode, data to be transmitted is inserted in a predetermined frame called STM (Synchronous Transport Module) frame, and is transmitted and received with synchronization established by using the STM frame. The STM frame includes a payload showing the data to be transmitted itself, and an overhead for a control of the data. The data to be transmitted is asynchronously inserted in the payload.
For this purpose, when transmission/reception of signal is made by using the asynchronously inserted data, a predetermined frame pattern (hereinafter often referred to as synchronization pattern) is allocated to a data row thereof to form a periodical frame bit.
For example, a frame format for the F2 byte has a simple frame structure having a small number of bits, in which a bit rate of the data row is 8 k b/s.times.8. Hence, in order to allocate the predetermined synchronization pattern in the frame format for the F2 byte, it is required to use the minimum number of bits.
However, data having the same synchronization pattern as the predetermined synchronization pattern used for the allocation may exist in a signal with an interval identical with that of the predetermined synchronization pattern. In such a case, a receiving side for receiving the above data may erroneously recognize a position of a header of the frame, resulting in possibility of pseudo-synchronization.
Thus, in order to prevent the pseudo-synchronization, there is a possible method including the steps of mounting two frame synchronization counters in the terminal apparatus, defining one counter as a counter for true synchronization and bringing the one counter into synchronization with a predetermined frame, and defining the other counter as a counter for pseudo-synchronization and bringing the other counter into synchronization with a frame other than the predetermined frame.
That is, in the system including the two counters as described above, when a certain error signal [such as CRC (Cyclic Redundancy Check) code] is outputted from a signal which has been brought into synchronization, the output signal triggers a discrimination between the true synchronization and the pseudo-synchronization.
However, in the above method, it is necessary to provide a special bit as error monitoring information in addition to the synchronization pattern allocated in the frame format for the F2 byte, resulting in a problem of an increase in number of bits other than those of the information to be transmitted (main information). That is, since the F2 byte has the frame structure with the small number of bits, the increase in number of bits used for information other than the main information reduces an amount of main information, thereby causing a reduction in transmission efficiency.